The present invention relates to a buffered crossbar switch, and in particular to changing the queuing buffer memory organization of a buffered crossbar switch.
Crossbar switches connect a plurality of input/output ports one to another. Data packets arriving at one of the input ports are routed to specific output ports.
Buffered crossbar switches have queuing buffers for temporarily storing data packets that cannot be routed to a specified output port instantly, which is possible since several concurrent routing operations may be performed.
Crossbar switches are frequently used in multi-processor computer systems with distributed memory architecture e.g. for linking processors with resources such as cache memory and other subsystems. Internet switch networks and similar high-performance communication networks also make use of crossbar switches.
In view of the high bit rate demands of the previously named applications, state of the art crossbar switches are designed for scalability to form expanded crossbar switches with a plurality of scalable crossbar switches working in parallel. This operation mode is referred to as expansion mode and it is characterized in that incoming data packets are divided into smaller portions each of which is processed by one of the scalable crossbar switches.
A general buffered crossbar architecture is depicted in FIG. 1 which will be referred to in the following explanations. This architecture is characterized by a plurality of input ports i1, i2, i3, i4, a plurality of output ports o1, o2, o3, o4, a plurality of input crossbars 7, each of which is connected to one of the input ports i1-i4 and a plurality of output crossbars 8, each of which is connected to one of the output ports o1-o4.
An intersection of an input crossbar 7 and an output crossbar 8 is called crosspoint. It can be seen that each crosspoint has a dedicated queuing buffer consisting of a buffer control 5 and a buffer memory 6. The arrows indicate the direction of data flow to/from the crossbars/queuing buffers.
The number M of queuing buffer entries greatly influences system performance. A sufficient number M of queuing buffer entries can avoid data loss due to blocking situations caused by multiple connections requesting the same switch resources such as e.g. the same output port.
When designing a crossbar switch, the constant size E of a queuing buffer entry is usually chosen with respect to the packet size of the data packets of a specific application.
Applications with data packets of different size, for instance E/4, must use one queuing buffer entry of the size E, too, for storing one data packet thus leaving 75% of the queuing buffer memory space unused.
Since queuing buffer memory is often provided as on-chip static random access memory (SRAM) within a switch chip, the inefficient way of using queuing buffer memory is one of the limiting factors for further reduction of the chip-size and hence the costs of a switch chip.